Moving from SoCs to Chiplets Could Help Extend Moore's Law

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As Moore's Law is again reaching its limits, several technologies, specifically chiplets, could be the key to extending it for many more years.

www.eetasia.com, Sept. 28, 2022 – 

As Moore's Law is again reaching its limits, several technologies, specifically Chiplets, could be the key to extending it for many more years.

Moore's Law, named after former Intel Corp. CEO Gordon Moore, states that the number of transistors in an integrated circuit doubles every two years. The prediction is widely used in the semiconductor industry, especially for microprocessors. Manufacturers use the "law" to set roadmaps and R&D targets.

Obviously, to continue this increasing density and miniaturization of semiconductors, many new technologies have appeared in the 55 years since Moore's Law was first proposed.

Historically, the photomask or reticle of a wafer was limiting the maximum size of a single chip. Therefore, manufacturers and designers had to use several chips to perform different functions. And, in many cases, they installed several chips for the same purpose, especially processor cores and memory modules.

Integration, especially for technologies such as System on a Chip (SoC) made it possible to combine several different components. SoCs enable faster communication between the parts, lower power consumption, improve optimization of wafer surface, reduce board real estate use, and lower costs.

Chiplets could add another step of performance extending Moore's Law

Recently, at TSMC's 2021 Open Innovation Platform, James Huang, Vice President of R&D, Alchip Technologies, argued that chiplets and advanced packaging provides competitive cost structure versus monolith SoCs while maintaining comparable performance and power consumption.

Huang cited two pieces of technology that will be critical to chiplet / packaging developments: One is TSMC's 3DFabric and CoWos combined technologies. The other is Alchip's APLink die-to-die (D2D) I/0.

Chiplets refer to the independent constituents which make up a large chip built out of multiple smaller dies. The increased cost of manufacturing on leading-edge process nodes is producing a reversal on the SoC integration trend. It is now becoming more advantageous to separate components into smaller "chiplets" to improve yield on each wafer.

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