MIPS Rolls Out Its First RISC-V Processor Core – It's a Big 'Un

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www.eejournal.com, Jan. 09, 2023 – 

Even though the company had telegraphed its big move, MIPS's adoption of the RISC-V ISA for its future processor cores hit me like a ton of bricks. MIPS is one of the heroes of the early RISC revolution, and the company has gone through a lot of ups and downs. Big ups. Big downs. Jim Turley discussed the MIPS announcement about joining the RISC-V gang last year. Last month at the RISC-V Summit, MIPS rolled out its first RISC-V core – the eVocore P8700 – an OOO (out of order) execution, multithreaded, 64-bit processor core designed for servers. The P8700 core will scale to 64 clusters with 512 processor cores in total, supporting 1024 harts (RISC-V hardware threads). In addition, MIPS announced its first P8700 customer, autonomous vehicle (AV) computer maker Mobileye.

The Mobileye announcement isn't all that surprising because Mobileye has been using MIPS CPU cores in its AV SoCs for a decade. With the new P8700 core, Mobileye gets an OOO execution speed boost, growing ecosystem support for RISC-V processor cores, an established and growing software and development tool library, and a growing army of knowledgeable programmers who are familiar with the architecture, having likely learned about the RISC-V architecture in college. In addition, the switch means that Mobileye's SoCs are no longer chained to a proprietary microprocessor architecture available from a single supplier. The company now finds itself awash in a rising sea of RISC-V processor core vendors. In fact, that's one of the biggest advantages that RISC-V offers: core vendor choice.

The MIPS saga began 40 years ago at Stanford University. John Hennessy and his graduate students caught wind of John Cocke's work at IBM on the 801 processor, which started in 1974. Back then, the Bell System needed an electronic telephone switch that could connect 300 calls per second. Figuring about 20,000 instructions per call setup and some overhead, the requirements called for a machine that could execute 12 million instructions per second (MIPS). That was about four times faster than IBM's fastest mainframe at the time, a System/370 Model 168.

Cocke proposed building a hot rod processor, much in the same way that car enthusiasts turned old 1930s automobiles into fast cars: ditch the weight and put in a big engine. Instead of cutting off fenders and pulling off the hood to reduce weight, IBM's 801 team ditched floating-point instructions, all memory-referencing instructions except for load and store, and, most especially, microcode. They built a big, pipelined execution engine out of pure hardware and created a board-level processor that hit 15 MIPS built out of Motorola MECL 10K small-scale logic chips. That execution rate exceeded the speed of IBM's System/370 Model 168 by 5X. (IBM first experimented with instruction pipelining with the Model 7030 Stretch mainframe computer, delivered to the Los Alamos National Laboratory in 1961.)

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