Area-efficient radiation-hardened 6 T SOI SRAM cell design using TDBC Transistors

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Single event upset (SEU) is a critical issue for the static random access memory (SRAM) exposed to irradiated environments. In this paper, an area-efficient 6 T SRAM cell design based on partially depleted silicon-on-insulator (PDSOI) technology is proposed to improve the ability to resist SEU using tunnel-diode body-contact (TDBC) transistors.

www.sciencedirect.com/, Mar. 01, 2023 – 

Compared with bulk‑silicon technology, SOI technology has the advantages of low power consumption, high integration and high speed [3]. SOI technology has been used for radiation hardening for many years due to its superior SEU resistance [4]. The existence of a buried oxide layer reduces the ionized charge collected in the sensitive areas when it is hit by high-energy particles, improving the anti-SEU capability of devices. Floating-body effects (FBEs) are a main concern in partially depleted (PD) SOI MOSFETs, resulting in the deterioration of electrical characteristics. In addition, the FBEs will reduce the SEU resistance of a device [5]. The most common scheme used to suppress FBEs is body contact, such as T-gate [6], I-gate [7], and body-tied-source structures [8]. The transistor with body contact can suppress parasitic bipolar amplification and reduce the transient current caused by high-energy particles bombardment. However, the area loss increases and the effective device width is reduced. In addition, with increasing channel width, the effect of body contact decreases. A tunnel-diode body-contact (TDBC) SOI structure is an area-efficient way to suppress FBEs based on source engineering [9]. This structure exhibits good performance in suppressing FBEs with large channel width. In general, the NMOS transistors inside the two inverters in a SRAM cell are more sensitive to SEU than PMOS transistors [10]. Therefore, the ability of SRAM to resist SEU can be improved by local reinforcement.

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