Single-Event Transient Study of 28 nm UTBB-FDSOI Technology Using Pulsed Laser Mapping

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www.mdpi.com, Feb. 02, 2023 – 

Single-event transient (SET)-induced soft errors are becoming a more significant threat to the reliability of electronic systems in space, especially for advanced technologies. The SET pulse width, which is vulnerable to SET propagation, is a critical parameter for developing SET mitigation techniques. This paper investigates the pulse-broadening effect in the process of SET propagation in logic circuits and the SET-sensitive region distribution in the layout using the pulsed-laser mapping technique in logic circuits implemented with 28 nm Ultra-Thin Body and BOX (UTBB) FDSOI technology. The experiments were carried out at the Naval Research Laboratory (NRL) to measure the SET-induced errors and map the SET-sensitive region distribution at various clock frequencies and laser energy levels. The results illustrate that the number of errors increases with the clock frequency and energy for combinational logic circuits and that the flip-flop SEU rate is less sensitive to clock frequency. The SET pulse-broadening effect was also observed using SET mapping for an OR gate chain at different laser energy levels. In addition, the simulation results revealed the mechanism of the SET pulse-broadening effect in an OR gate chain.

Keywords: single-event transient; SET; 28 nm UTBB FDSOI; pulse broadening; pulse laser; SET mapping

1. Introduction

One type of soft error, the Single-Event Transient (SET), is becoming an increasing threat to the reliability of electronic systems as device dimensions are downscaled to nanometers in space applications. These types of transients can propagate to downstream circuits and lead to electronic system errors, several of which have been previously observed in other works [1,2,3,4,5,6]. Fully Depleted Silicon-On-Insulator (FDSOI) technology has become one of the most popular candidate technologies used in space for modern process nodes because of its superior resilience to the single-event effect, which is the result of the extremely smaller charge-collection volume [7,8,9,10,11]. It has been proven that the soft error rate (SER) with a 28 nm Ultra-Thin Body and BOX (UTBB) is almost two orders of magnitude lower than with similar 28 nm bulk technology [8,9,10,11,12,13,14]. Previous studies have focused on the Single-Event Upset (SEU) characteristics, total-dose ionizing responses, and simulations of FDSOI technology [15,16,17,18,19]. However, it was found that soft errors resulting from SETs in combinational logic circuits surpassed those resulting from SEUs in storage circuits, such as flip-flops and SRAM, when the combinational logic circuit operates at a high frequency [6,20,21,22,23]. Moreover, errors induced by SETs in logic circuits cannot be eliminated by error-correcting codes (ECCs), which are usually adopted in SEU mitigation designs [6,22,23,24,25,26]. In addition, it is still unclear whether the trend is the same for 28 nm UTBB-FDSOI technology. Therefore, it is important to understand the SET characteristics and their impact on circuit designs using 28 nm UTBB-FDSOI technology.

In this paper, a chip manufactured using 28 nm UTBB FDSOI technology is used to directly evaluate the SET effects, and the chip's distribution map of the SET-sensitive area is illustrated. The chip is designed with Vernier circuits [27], two test circuits with different characteristics, and an OR2 gate circuit as the target circuit. The two test circuits are Pulse Capture and CREST (Circuit for Radiation Effects Self-Test) circuits. The simulation was conducted using the Cadence Spectre tool, and the proposed SET measurement circuits, test structures, and SPICE simulation model were previously verified in another study [28]. For SET mapping in OR2 gate chains, a propagation-induced SET pulse-broadening effect was observed in the pulsed laser experiment. It was found that the SET pulse widths depended on the distance of the SET production position from the SET detection circuit. The reasons for OR2 gate chains' sensitivity to the pulse-broadening effect are also studied using post-layout SPICE simulations. The SER in the CREST circuits, which consist of flip-flops and combinational logic gates, is visualized by showing the relationship between SET- and SEU-induced SERS and the clock frequencies in these circuits.

The remainder of this paper is organized as follows. Section 2 describes the details of the SET test circuits and experimental setup; Section 3.1 presents the SET sensitivity distribution of an OR gate chain and a CREST circuit with laser mapping; Section 3.2 presents the reasons for the pulse-broadening effect in an OR gate chain using simulations; and Section 4 presents the conclusions of the study.

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