TSMC adds two variants to 2nm node; will Intel catch up?

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Taiwan's mega-fab will add two variants to its N2 technology in 2026: N2P with backside power delivery and N2X for HPC processors.

www.ednasia.com/, May. 10, 2023 – 

TSMC's 2-nm chip fabrication process, widely known as N2, is on track for production in 2025, according to the details provided by the company at its 2023 North America Technology Symposium in Santa Clara, California. Taiwan's mega-fab will also add two variants to its N2 technology in 2026: N2P with backside power delivery and N2X for high-performance computing.

The N2 and its variants will be the first manufacturing nodes at TSMC to employ the gate-all-around (GAA) transistors–which TSMC calls nanosheet transistors–to boost performance, energy efficiency, and transistor densities for logic, SRAM, and analog circuits. The GAA technology facilitates lower leakage current as gates are present on all four sides of the channel. Moreover, GAA transistors boost the ability to adjust the channel width for higher performance or lower power consumption.

At the symposium, TSMC claimed that its new nanosheet transistors already meet 80% of the target performance specs, while the average yield of a 256-Mb SRAM is currently above 50%. And the semiconductor foundry still has two years to improve these figures.

According to TSMC, N2 will offer 10% to 15% more performance at the same power as N3 or a 25% to 20% power reduction at the same clocks. The fab also claims that for a mixed chip–comprising logic, SRAM and analog–N2 will accomplish 15% higher density than N3E, an enhanced version of the N3 fabrication node.

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