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Chiplet interconnect handles 40 Gbps/bump

www.edn.com, May. 23, 2023 – 

Eliyan announced the first silicon implementation of its NuLink PHY chiplet interconnect, operating at 40 Gbps/bump to enable a beachfront bandwidth of 2.2 Tbps/mm. Fabricated on TSMC's 5-nm process node, the NuLink chip uses standard organic packaging with a 130-µm bump pitch. With finer bump pitches, the bump-limited NuLink PHY can deliver as much as 3 Tbps/mm.

The successful silicon implementation of NuLink technology demonstrates that it can be applied in organic substrate packaging to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations that employ advanced packaging technologies. For example, NuLink eliminates the need for silicon interposers (in most applications) that limit overall system-in-package (SiP) size and ultimately constrain performance. Without the drawbacks of advanced packaging, the NuLink chiplet interconnect allows a greater number of cores and compute performance per power at lower cost and higher yield.

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