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Interconnect, D2D, C2C IP Catalog

Chip to Chip (5)

Die-to-die (32)

Intra SoC Connectivity (10)

Network Interconnect (15)

1

2-16Gbps Die-to-Die (D2D) Multi-Protocol IO Supporting BOW, OHBI and UCIe

AresCORE is a market leading extremely low-power, low-latency interface IP designed by Alphawave IP for very high bandwidth connections between two dies that are on the same package.

2

25-112Gbps Extra Short-Reach (XSR) Multi-Standard SerDes (MSS)

The Alphawave DieCORE delivers the world s highest density, lowest power die-to-die connectivity solution for MCMs based on OIF XSR/USR serial standards. The DieCORE is a companion IP to the AlphaCOR...

3

D2D PHY (Die-to-Die Interface)

Die-to-Die (D2D) PHY IP is based on HBM electrical specification and will also be compatible with upcoming interface standards. It is used specifically for heterogenous chiplet solutions in wired comm...

4

D2D Controller IP (Die-to-Die Interface)

OpenFive s Die-to-Die (D2D) Controller IP is targeted for heterogenous chiplet solutions in wired communications, AI and HPC applications. With recent advances in package technologies, it is possible ...

5

DesignWare Die-to-Die Controller IP with AXI Interface

The DesignWare Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accelerator, networking and high-performance comput...

6

DesignWare Die-to-Die Controller IP with AXI Interface

The DesignWare Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accelerator, networking and high-performance computing...

7

DesignWare Die-to-Die PHY IP in TSMC N7 Process

The DesignWare Die-to-Die PHY IP enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, and networking applications. The low-latency...

8

16G UCIe Advanced PHY for TSMC 3nm

UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

9

16G UCIe Standard PHY for TSMC 3nm

UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

10

16G UCIe Standard PHY for TSMC 7nm

UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

11

40G Ultralink D2D PHY for GF12LP+

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

12

40G Ultralink D2D PHY for Samsung 7LPP

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

13

40G Ultralink D2D PHY for TSMC 3nm

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

14

40G Ultralink D2D PHY for TSMC 5nm

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

15

40G Ultralink D2D PHY for TSMC 7nm

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

16

Mobiveil RapidIO Controller (GRIO)

Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface on the system side.

17

Universal Chiplet Interconnect Express (UCIe 1.0) Controller

Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols

18

1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)

eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ultra-high speed SerDes IP is adopted by global Ti...

19

1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency

Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies. eTopus is the pioneer on PAN4 ADC/DSP-based SerDes, the first startup demonstrated 56Gb...

20

CodaCache Last Level Cache IP

CodaCache is a configurable, standalone, non-coherent cache IP that delivers unique business value through its advanced last-level cache (LLC) architecture, improving system performance, data locality...

21

FlexNoC 5 Network-on-Chip (NoC)

Arteris FlexNoC 5 network-on-chip (NoC) physically aware interconnect IP improves development time, performance, power consumption, and die size of system-on-chip (SoC) devices for mobile, automotive,...

22

FlexNoC 5 Option For Scalability and Performance Critical Systems

Arteris IP FlexNoC Performance Option accelerates development of next-generation deep neural network (DNN) and machine learning systems. Automate and optimize the networks while efficiently implementi...

23

FlexNoC Resilience Package

The Arteris FlexNoC Resilience Package provides hardware-based data protection for increased SoC reliability and functional safety.

24

FlexWay Interconnect IP

FlexWay 5 from Arteris is an essential entry-level IP generator for cost-efficient, high-performance network-on-chip (NoC) designs. It revolutionizes SoC development with optimized interconnects, r...

25

High speed NoC (Network On-Chip) Interconnect IP

OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip Interconnect, which delivers exceptional performance...

26

Innovative Ultra-High-Speed Chiplet Solution

Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chips as if they were all on the same bus. Chiplets, d...

27

Multi-Die interLink (GLink 2.3) IP

GUC multi-die interLink (GLink) IP provides world’s best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a package for applications such as High Performance ...

28

Ncore 3 Coherent Network-on-Chip (NoC)

For scalable and area-efficient heterogeneous cache coherent systems.

29

Ncore 3 Coherent Network-on-Chip (NoC)

For scalable and area-efficient heterogeneous cache coherent systems. The Arteris Ncore Cache Coherent Interconnect IP offers unparalleled scalability, configurability, and, with the Ncore Safety Opt...

30

TSMC CLN6FF/7FF Die-to-Die Interface PHY

IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes per slice and supports 8 slices in one PHY. Each Tx/...

31

Analog I/O + ESD protection for Die-2-die interfaces

Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven)

32

Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers

The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.

33

2GBps Low Power D2D Interface

Custom die-to-die high-speed interface in 28nm process technology. The I/O cells are defined as TX only, and RX only, and have two modes of operation, standard full rail to swing, or a custom low nois...

34

5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support

This IP is optimized for AI/ML workloads and lowest possible latency.

It is not meant to be a generic 1G to 10G MAC – it only supports 5G and 10G operation.

35

600MBps Low Power D2D Interface in 16nm

Custom die-to-die interface in 16nm process technology. The I/O cell is bi-directional and has two modes of operation: standard rail-to-rail swing or a custom low-noise pseudo-differential interface. ...

36

BlueLynx Executable Generator Technology

BlueLynx™ technology revolutionizes the game in silicon design and engineering. Using proprietary technology, Blue Cheetah eliminates inefficiencies inherent in traditional silicon design processes while maintaining complete integrity.

37

Bunch of Wires [BoW] PHY IP

Blue Cheetah's Bunch of Wires [BoW] PHY IP design incorporates the maximum benefit of the Open Compute Project's (OCP) inter-chiplet PHY specification, targeting best in class power, performa...

38

Coherent Network-on-Chip (NOC)

Scalable and area efficient interconnect solution optimized for memory coherent systems

39

Coherent Network-on-chip (NoC) IP

C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous existence of both coherent and non-coherent traffic. It...

40

Coherent Network-on-chip (NoC) IP

C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous existence of both coherent and non-coherent traffic. It...

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