Interconnect, D2D, C2C / Intra SoC Connectivity IP Catalog

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Interconnect, D2D, C2C IP Catalog

Chip to Chip (5)

Die-to-die (32)

Intra SoC Connectivity (10)

Network Interconnect (15)

1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)

eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ultra-high speed SerDes IP is adopted by global Ti...

1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency

Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies. eTopus is the pioneer on PAN4 ADC/DSP-based SerDes, the first startup demonstrated 56Gb...

FlexNoC Resilience Package

The Arteris FlexNoC Resilience Package provides hardware-based data protection for increased SoC reliability and functional safety.

Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers

The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.

CXL 3.0 Dual Mode Controller

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL cards has same form factor as PCIE , and can be used ...

CXL Host Device Dual mode controllers

Primesoc s CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.

1 - 33Gbps PCIe Gen1-5 SerDes PHY (AXLinkIO MR)

The AXLinkIO MR IP utilizes the silicon-proven AXLinkIO transceiver architecture for medium-reach and PCIe type of channel links.

CXL (Compute eXpress Link) 3.1 IP

The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch. The IP supports all features of the CXL 3.1 specifications and is fully backward compatible...

Highly configurable Interlaken ILA & ILK

Tamba Networks offers a highly configurable Interlaken ILA and ILK core. The core is compliant with the Interlaken and Interlaken look-aside specifications, and targets FPGA and ASIC operation. The S...

RAMLinx interconnect

RAM of any size and kind in your EFLX® array

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