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33 "Interconnect, D2D, C2C" Solutions

1
112G XSR Multi-protocol SerDes PHY
A high-bandwidth, ultra-low power SerDes PHY solution for extremely short reach (XSR) 112G inter-die connections in system in package (SiP) devices serving next-generation networking and hyperscale da...

2
CXL (Compute Express Link) Dual Mode Controller
Highly Configurable, Technology Independent, System Validated.

3
Mobiveil RapidIO Controller (GRIO)
Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface on the system side.

4
XpressLINK - Controller IP for CXL
XpressLINK™ is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation.

5
D2D PHY (Die-to-Die Interface)
Die-to-Die (D2D) PHY IP is based on HBM electrical specification and will also be compatible with upcoming interface standards. It is used specifically for heterogenous chiplet solutions in wired comm...

6
D2D Controller IP (Die-to-Die Interface)
OpenFive's Die-to-Die (D2D) Controller IP is targeted for heterogenous chiplet solutions in wired communications, AI and HPC applications. With recent advances in package technologies, it is possible ...

7
TSMC CLN6FF/7FF Die-to-Die Interface PHY
IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes per slice and supports 8 slices in one PHY. Each Tx/...

8
25-112Gbps Short-Reach PHY
The Alphawave DieCORE delivers the world’s highest density, lowest power die-to-die connectivity solution for MCMs based on IEEE XSR/USR serial standards. The DieCORE is a companion IP to the AlphaCO...

9
C2C Chip to Chip Link Inter-chip Connectivity IP
The purpose of inter-chip connectivity IP is to connect two different chips together to share computing resources, limit chip-to-chip latency, or maintain the highest possible chip-to-chip bandwidth. ...

10
FlexLLI MIPI Low Latency Interface (MIPI LLI) Digital Controller Interchip Connectivity IP
Arteris FlexLLI digital controller IP is the industry s first and only silicon-proven implementation of the MIPI Low Level Interface (LLI) specification. Arteris FlexLLI digital controller IP can con...

11
FlexNoC Network on Chip SoC Interconnect IP
FlexNoC is the ideal interconnect for SoC designs requiring higher performance with minimum area and power. Its flexible architecture makes it the right solution for interconnects with both low latency requirements and high throughput needs. FlexNoC provides support for the additional features that today SoCs require, such as clock domain conversion, width conversion, security, and multi-protocol support. The product supports the AMBA (APB, AHB, AXI) protocols and OCP and can easily be extended to support proprietary protocols.

12
FlexNoC Resilience Package
The Arteris FlexNoC Resilience Package provides hardware-based data protection for increased SoC reliability and functional safety.

13
FlexNoC Resilience Package IP
The Arteris FlexNoC Resilience Package is a complementary product to Arteris FlexNoC fabric IP. It implements hardware resilience features essential for systems-on-chip (SoCs) targeted for mission-cri...

14
Innovative Ultra-High-Speed Chiplet Solution
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chips as if they were all on the same bus. Chiplets, d...

15
Ncore Cache Coherent Interconnect IP
For scalable and area-efficient heterogeneous cache coherent systems.

16
PIANO 2.0 Automated Interconnect Timing Closure Technology
PIANO 2.0 solves back-end timing problems with technology that works earlier in the SoC design flow, thereby reducing schedule risk.

17
Analog I/O + ESD protection for Die-2-die interfaces
Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven)

18
DesignWare Die-to-Die Controller IP with AXI Interface

The DesignWare Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accelerator, networking and high-performance comput...


19
DesignWare Die-to-Die Controller IP with AXI Interface
The DesignWare Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accelerator, networking and high-performance computing...

20
DesignWare Die-to-Die PHY IP in TSMC N7 Process
The DesignWare Die-to-Die PHY IP enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, and networking applications. The low-latency...

21
1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ultra-high speed SerDes IP is adopted by global Ti...

22
33G Die-to-Die SerDes PHY (12nm 16nm)
The AnalogX AXDieIO IP utilizes the silicon-proven AXLinkIO transceiver architecture for die-to-die, in package, type of channel links.

23
ANOC - Asynchronous Network on Chip IP
ANoC, a clock-less interconnect solution, aimed at simplifying the design of complex SoC, using standard synchronous tools & flow

24
AXLinkIO MR
The AXLinkIO MR IP utilizes the silicon-proven AXLinkIO transceiver architecture for medium-reach and PCIe type of channel links.

25
BlueLynx Executable Generator Technology
BlueLynx™ technology revolutionizes the game in silicon design and engineering. Using proprietary technology, Blue Cheetah eliminates inefficiencies inherent in traditional silicon design processes while maintaining complete integrity.

26
Bunch of Wires [BoW] PHY IP
Blue Cheetah's Bunch of Wires [BoW] PHY IP design incorporates the maximum benefit of the Open Compute Project's (OCP) inter-chiplet PHY specification, targeting best in class power, performa...

27
CXL Host Device Dual mode controllers
Primesoc s CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.

28
Highly configurable Interlaken ILA & ILK
Tamba Networks offers a highly configurable Interlaken ILA and ILK core. The core is compliant with the Interlaken and Interlaken look-aside specifications, and targets FPGA and ASIC operation. The S...

29
Interconnect Technology
EXTOLL introduces a new interconnection network architecture for High-Performance Computing, which brings a rich set of features to the HPC application space.

30
Nutcracker XSR Connectivity Chiplet

Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to next generation of advanced process geometries...


31
RAMLinx interconnect
RAM of any size and kind in your EFLX® array

32
Standard Compliant AMBA AXI SoC Interconnect, Soft IP
The AMBA AXI interface is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for a high-speed submicron interconnect. The AXI protocol ...

33
WISHBONE SoC Interconnect

IDesignSpec™ is an award winning product that helps IP/SoC design architects & engineers to create simple yet powerful specification in MS Word, Excel, Libre Office or plain text. The specifi...


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