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Multi-Die interLink (GLink 2.3) IP


GUC multi-die interLink (GLink) IP provides world’s best class solution for high-bandwidth,
low-power, low-latency multi-channel interconnection in a package for applications such
as High Performance Computing, Data Center, Artificial Intelligence and Networking.

The IP utilizes single-ended DDR clock forwarding parallel bus interface with TSMC’s
RDL-based InFO (Integrated-Fan-Out) or CoWoS (Chip-on-Wafer-on-Substrate) up to
8/16Gbps per lane which consumes only 0.25pJ/bit. One slice has 32 full-duplex lanes
and one PHY has 8 slices with 2/4Tbps maximum bandwidth. For the next generation
GLink, one slice will have 56 full-duplex lanes and one PHY has 8 slices with 7.5 Tbps
maximum bandwidth.

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