Interconnect, D2D, C2C / Network Interconnect SoC Catalog

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Interconnect, D2D, C2C Catalog

Chip to Chip (3)

Die-to-die (28)

Intra SoC Connectivity (9)

Network Interconnect (10)

Mobiveil RapidIO Controller (GRIO)

Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface on the system side.

CodaCache Last-Level Cache IP

It is a configurable, standalone, non-coherent cache IP that delivers unique business value through its advanced last-level cache (LLC) architecture, improving system performance, data locality, sc...

FlexNoC 5 Network-on-Chip SoC Interconnect IP

Arteris IP FlexNoC 5 network-on-chip (NoC) physically aware interconnect IP improves development time, performance, power consumption, and die size of system-on-chip (SoC) devices for mobile, automoti...

FlexWay Interconnect IP

FlexWay 5 from Arteris is an essential entry-level IP generator for cost-efficient, high-performance network-on-chip (NoC) designs. It revolutionizes SoC development with optimized interconnects, r...

Ncore Cache Coherent Interconnect IP

Multicore SoC design challenges.

Key challenges in multicore system-on-chip (SoC) designs include efficient inter-core communication and synchronization, maintenance of cache coherence...

Coherent Network-on-Chip (NOC)

Scalable and area efficient interconnect solution optimized for memory coherent systems

Coherent Network-on-chip (NoC) IP

C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous existence of both coherent and non-coherent traffic. It...

Coherent Network-on-chip (NoC) IP

Interconnect Technology

EXTOLL introduces a new interconnection network architecture for High-Performance Computing, which brings a rich set of features to the HPC application space.

Non-Coherent Network-on-Chip (NOC)

Performance (bandwidth and latency) optimized non-coherent NOC solution that significantly reduces silicon wire utilization, resulting in power and area efficient ICs

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