Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...
You are here : design-reuse-embedded.com  > Interconnect, D2D, C2C  > Intra SoC Connectivity

1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency


Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies.

eTopus is the pioneer on PAN4 ADC/DSP-based SerDes, the first startup demonstrated 56Gbps PAM4 in 2016. The system architecture has been proven and enhanced for 3 generations to 112Gbps PAM4 in 7 and 6nm. This IP is optimized for low power (<6pj/bit) and latency < 5ns.

Our unique and patented DSP algorithms provide excellent scalability to support short reach optical channel to long reach copper like backplane and DAC cables with superior Bit Error Rates (BER) and extremely robust Clock Data Recovery (CDR) as featured in International Solid State Circuits Conference (ISSCC 2021).

Partner with us

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2024 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.