Chiplets advancing one design breakthrough at a time

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What's the state of chiplet technology today? As the cost advantages of silicon process scaling driven by Moore's law start to dwindle, will the chiplet approach replace system-on-chip (SoC) designs with multi-die heterogeneous implementations? Are small steps toward implementing chiplet technology sufficient for this landmark semiconductor industry undertaking?

www.edn.com/, Jun. 13, 2023 – 

There is no simple answer to these questions yet. But one thing is clear: multi-die architectures are becoming increasingly critical in handling the needs of compute-intensive applications in data centers, cloud computing, and generative artificial intelligence (AI), technologies that require large amounts of memory and fast inter-chip communications.

Then there are automotive and gaming applications that mandate much more reliable and cost-effective solutions than what the current advanced packaging solutions can offer. So, where do the high-performance and highly scalable multi-die architectures for compute-intensive applications actually stand? After years of existence as a small niche, we finally see a few significant breakthroughs in 2023.

Successful silicon implementations are starting to demonstrate the full benefits of the multi-die architectures without constraints imposed by advanced packaging such as size limitations of silicon interposers. The chiplet-based systems in standard organic packages can now achieve similar bandwidth, power efficiency, and latency compared to advanced packaging technologies without the drawbacks of these complex and expensive solutions.

The chiplet-based systems encompassing larger system-in-package (SiP) solutions enable higher performance per power at considerably lower cost and higher yield. The SiP-based approach also eliminates the need for silicon interposers, which limit overall SiP size and constrain the amount of memory and compute cores in a package.

The Yole Group estimates that the chiplet-based SIPs market will exceed $135 billion by 2027. However, the economics of adopting a chiplet approach for IC design are tightly linked with the cost and maturity of the interconnect and packaging solutions, noted John Lorenz, senior analyst for computing and software solutions at Yole Intelligence.

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