Samsung tapes out 2nm backside routing test chip

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Cadence Design Systems has had its tools certified for the 2nm process at Samsung Ondry with digital, custom analog and backside routing.

www.eenewseurope.com/, Jul. 04, 2023 – 

The digital and custom analog design flows are certified for the SF2 2nm and SF3 3nm processes, while a complete backside routing solutions enable next-generation high-performance chips for mobile, automotive, AI and hyperscale applications.

The backside implementation flow is already proven with a successful SF2 test chip tapeout. This is a key capability for 2nm designs that can be constrained by a lack of routing for Samsung, Intel and TSMC, instead routing on the back of the wafer and using vias to connect power lines.

The certification means engineers can design ICs with PDKs based on certified SF2 and SF3 flows using custom and analog tools, including AI-based Virtuoso Studio.

The flow includes the Genus Synthesis Solution, Modus DFT Software Solution, Innovus Implementation System, Quantus Extraction Solution and Quantus Field Solver, Tempus Timing Signoff Solution and Tempus ECO Option, Pegasus Verification System, Liberate Characterization Portfolio, Voltus IC Power Integrity Solution and the Cadence Cerebrus Intelligent Chip Explorer.

Cell-swapping support helps designers align cell pins for direct connections to conserve routing resources while support for mixed-row solutions in various combinations to maximize area-based design rules as well as the ability to place and refine traces using mask-shifted cells and horizontal half-track shifted cells to reduce displacement. There is also support for various rectilinear standard cells to achieve higher density and reduced IR drop due to the insertion of enhanced, trim-aware via staples.

The backside routing relies on the Innovus GigaPlace engine that automatically places and legalizes a nano through silicon via (nTSV) structure, allowing a connection between frontside and backside layers. The Innovus GigaOpt engine uses backside layers for timing-critical long wires to improve chip performance while the Innovus NanoRoute engine inherently supports backside routing based on rules in the technology's Library Exchange Format (LEF).

The Quantus Extraction Solution fully supports backside layers to enable the Tempus Timing Solution to sign off designs with a mix of frontside and backside layers, delivering reduced voltage drop on the power distribution mesh and improved routability on the frontside metal layers.

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