First 22nm FGPA with hardened RISC-V cores

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Gowin Semiconductor has hardened a RISC-V core and peripherals and embedded them into its latest 22nm FPGA.

www.eenewseurope.com/, Sept. 02, 2023 – 

The GW5AST-138 FPGA uses the A25 RISC-V CPU IP and AE350 peripheral subsystem from Andes Technology for its first complete RISC-V FPGA.

In the same way as hardened ARM cores were added to previous Gowin FPGAs, the A25 and peripherals, including a SERDES interface, avoid consuming any FPGA resources. This allows a hardware team to populate the FPGA with a design while the software team can concurrently create application code based on the RISC-V ecosystem.

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The A25 hard core runs at 400MHz and supports the RISC-V P-extension DSP/SIMD ISA (draft), single- and double-precision floating point and bit-manipulation instructions, and MMU for Linux based applications.

The AE350 AXI/AHB-based subsystem comes with level-one memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller, AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components pre-integrated together as a system design.

A DDR3 controller and SPI-Flash controller in the FPGA fabric back up the A25's 32KByte I-Cache and D-Cache after cache misses and off chip DDR3 provides data memory. An SPI-Flash contains the A25's instruction memory with the code copied from SPI-Flash into DDR3 and cache upon boot-up).

Alongside the hard instantiated IP, the GW5AST-138 FPGA fabric provides 138K LUTs for custom design implementation and Gowin provides an FPGA hardware development environment for the Arora V. The environment supports multiple RTL-based programming languages, synthesis, placement and routing, bitstream generation and download, power analysis and in-device logic analyzer.

However this is not the first FPGA with hardened RISC-V cores. Microchip has a PolarFire FPGA with four RISC-V cores for processing and two for housekeeping, which has been used in a system on module (SoM) from Aries Embedded in Germany.

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