MEEP: An HPC Systems Development Platform for RISC-V Based HW/SW Co-Design

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BARCELONA, Spain, September 22, 2023 – After three and a half years of research, the European-funded Marenostrum Experimental Exascale Platform (MEEP) project has successfully concluded its mission of promoting innovation and collaboration in advanced platform development. MEEP has thrived as a cutting-edge platform designed to offer novel and reusable IPs tailored for FPGAs and ASICs. Emphasizing heightened productivity and adaptable frameworks, MEEP serves as a co-design testing ground for software and hardware developers, equipping them with valuable resources to delve into new architectural concepts, validate benchmark performance, and demonstrate future system concepts.

www.hpcwire.com/, Sept. 22, 2023 – 

Embracing Open Possibilities

MEEP's relentless embrace of the European RISC-V architecture was central to its mission. RISC-V is an open standard instruction set architecture (ISA) that champions collaborative efforts and design autonomy. This alignment liberates MEEP from the confines of proprietary ISAs, symbolizing a paradigm shift towards innovation and shared evolution. The FPGA-based emulation capabilities are inherent to MEEP, illuminating the dynamic capacities of individual or multiple accelerators spanning nodes.

Unleashing the Accelerated Compute and Memory Engine Accelerator (ACME)

Accelerated Memory and Compute Engine (ACME), a self-hosted accelerator, is the core of the MEEP architecture. ACME holds immense potential for memory bandwidth-constrained tasks and compute-bound operations. Its architecture comprises two fundamental building blocks: a computational engine and a memory engine, working in tandem to optimize performance across different workloads. The computational engine handles data manipulation involving scalar and vector components, while the memory engine efficiently manages memory transactions and accesses, leading to energy savings and higher performance. The ACME architecture is underpinned by a multi-core RISC-V processor, tailored to handle scalar and vector instructions, and further integrates co-processors to enhance its performance capabilities.

The three accelerators –the Vector Processing Unit (VPU), the Systolic Array for video processing (SA-HEVC), and the Systolic Array for Neural Network (SA-NN)– share identical interfaces, simplifying control and programming. Furthermore, the uniform interfaces across these three vector accelerators streamline data flow control and programming in different operational modes (classic and acme) while laying the foundation for potential future accelerator exchanges. This demonstrates ACME's versatility as an accelerator capable of addressing various problem types, including vector architecture for HPC, SA-HEVC image and video processing, and SA-NN graph processing. Additionally, using systolic arrays has resulted in the development a customized vector extension, which has proven to enhance performance.

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