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Samsung Seen Stumbling at Silicon's Leading Edge
www.eetimes.com, Dec. 20, 2023 –
Samsung, which last year claimed chip tech leadership by being the first to start production at the 3-nm node, is struggling to find customers, some of whom told EE Times the foundry's leap ahead is too risky.
AI chipmakers Alphawave, Rebellions and Tenstorrent told EE Times they've chosen Samsung as their 4-nm foundry because the chipmaker is cutting prices and adding services to win customers from top rival Taiwan Semiconductor Manufacturing Co. (TSMC).
"At 4-nm FinFET, they [Samsung execs] have stabilized that process," one of the Samsung customers told EE Times, speaking on condition of anonymity. "This isn't 3-nm gate-all-around [nanosheet], where they still seem to be struggling a little bit to get yield and reliability."
Samsung is wrestling with 3 nm because nanosheet 3D chip architecture was one of several steps too far, SemiAnalysis chief analyst Dylan Patel told EE Times. TSMC, which has been making 3-nm chips for Apple and MediaTek since early this year, won't adopt nanosheet until 2025.
"If you look at Samsung, their 4 nm was less dense than TSMC's 5 nm," Patel said. "They're jumping straight to something that is 3-nm density, also with the nanosheet structure. That's one of the biggest hurdles."
Samsung hasn't worked out the "M0" contacts between metal interconnect and transistor layers at the 3-nm node, he said. "The metal-layer zero contacts have a lot of stochastics," he said, noting a recent teardown of Samsung chips by research firm TechInsights.
TSMC and Intel have taken more cautious steps toward nanosheet, Patel said. TSMC will introduce nanosheet with its 2-nm node in 2025.
"If you look at what TSMC is indicating about 2 nm, it's not a massive physical shrink versus 3 nm," he said. "If you look at Intel's [advanced-node] 18A and 20A, it's not really a physical shrink versus TSMC's 3 nm. It's more a nanosheet change."
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