TSMC reaffirms path to 1-nm node by 2030 on track

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www.edn.com, Jan. 01, 2024 – 

TSMC, while reaffirming its commitment to launch the 1-nm fabrication process in due time, is confident it will overcome technological and financial challenges all the way to 2030. The Hsinchu, Taiwan-based foundry showcased its technology roadmap for 2 nm, 1.4 nm, and 1 nm process nodes at the recent IEDM conference.

It's worth mentioning that EUV lithography tool supplier ASML expects to reach 1-nm process technology in 2028. On TSMC's part, it has opened a research and development center in Hsinchu, Taiwan, where 7,000 researchers are working on novel materials and transistor structures for 1-nm chips.

Concurrent to work on a 1-nm process node for monolithic chips, TSMC is also focusing on advancements in packaging technologies to produce multi-chiplet solutions capable of packing more than a trillion transistors by 2030. TSMC plans to put a trillion chips on a package using multiple 3D-stacked chiplets.

Intel catching up

Like TSMC, Intel is also concurrently focusing on cutting-edge process nodes as well as chiplets and advanced packaging technologies to put a trillion transistors on a package. However, while TSMC plans to ride the 2-nm train by 2025, Intel claims that it will leapfrog Taiwan's mage-fab by launching its 2-nm process node called A20 in 2024. Yet, as we enter 2024, it's still to be seen if Intel can meet its 2-nm deadline. Intel has announced the production of a 20A-based CPU called Arrow Lake in 2024.

Likewise, the Santa Clara, California-based chip giant plans to advance to a 1.8-nm process node–or Intel 18A–in 2025. Next, by 2028, Intel plans to develop a 1.4-nm process node it calls A14; on the other hand, while TSMC earlier claimed to complete the 1.4-nm process node development by 2026, it's now hinting about a 1.4-nm node to be ready by 2028.

Samsung, another archrival of TSMC, is also confident that its 1.4-nm process technology will come into its own in 2027. Still, the company more visible in the 1-nm fray besides TSMC is based in Japan, Rapidus, a Japanese government-funded startup fab.

Rapidus joins the fray

Rapidus, which previously engaged with IBM and Belgium's imec for the design of a 2-nm fabrication process, has now joined hands with the University of Tokyo and French research institute CEA Leti to develop a 1 nm node in the 2030s. The collaboration first aims to produce a 1.4-nm process by 2027.

Here, Leti will focus on exploring novel transistor structures while Rapidus and other Japanese partners, including Riken Research Institute, will contribute through staff exchanges, fundamental research sharing, and the assessment and testing of prototypes.

Leti's role regarding new transistor structures will be crucial because industry observers anticipate that vertically stacked complementary field effect transistors (CFETs) may replace gate-all-around (GAA) FET technology at 1.4 nm and 1 nm nodes.

Rapidus' tie-up with IBM and imec is expected to lead to 2-nm pilot chip production in 2025 and high-volume production in 2027. Rapidus entry in the manometer race with a labyrinth of partnerships and alliances shows that while TSMC has become an undisputed leader in chip fabrication, the field is gradually getting crowded. And that's good for chip vendors and the semiconductor industry at large.

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