MIPS snags top SiFive brains to amp up RISC-V business

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Chip designer MIPS has picked up two former senior staff from SiFive in a bid to boost its RISC-V development efforts.

theregister.com/, Jan. 03, 2024 – 

MIPS, the company that created the processor architecture of the same name, is now looking to the RISC-V open instruction set architecture for new products under the eVocore name. The eVocore P8700 has been shipping since December 2022.

The company has now appointed Drew Barbier as VP of products and Brad Burgess as chief architect to help drive further development and market take-up of its products.

The duo were formerly at SiFive, one of the more prominent companies in the RISC-V landscape, which underwent a dramatic restructuring of its business last year with 20 percent of staff laid off. This was understood to include some of the management team as well as engineers.

Burgess was a chief CPU architect at Samsung, and a fellow at SiFive, and has upwards of three decades of experience with various processor architectures including Arm, 68000, PowerPC, and x86, as well as RISC-V. He will be responsible for development of all new key product designs, MIPS told us.

Barbier served for more than six years at SiFive as senior director of product management, and also previously worked for Arm and Analog Devices. He will oversee MIPS' product roadmap.

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