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VISC: The New Coprocessing RISC-V Architecture for AI Efficiency

Red Semiconductor has announced the availability of its Versatile Intrinsic Structured Computing (VISC) architecture for RISC-V. VISC is an extension to RISC-V IP that accelerates complex algorithms and adds parallel processing to improve AI operations in edge computing.

www.allaboutcircuits.com/, Apr. 13, 2024 – 

One of RISC-V's strong value points is the amount of customization possible within the standard. Red Semiconductor has taken advantage of that aspect to develop a licensable high-performance architecture. The VISC instruction set architecture (ISA) adds edge AI, autonomy, and cryptography capabilities to open-source RISC-V. The code is optimized for FPGA and ASIC SoCs.

What Is VISC?

VISC is a vector processing engine built within a RISC-V processor chip. It has its origins in open-source Libre-SOC. Libra-SOC is designed to bring complex algorithms, typically reserved for GPUs, to microcontrollers and small CPU-based devices. Red Semiconductor built VISC upon Libra-SOC and the open-source CPU RISC-V architecture. The result is a CPU core that is compatible with RISC-V and has vector AI processing extensions.

Red Semiconductor claims VISC performs higher and with less power than other small system/high computation-need processing devices. It improves performance by using hardware elements to deconstruct algorithms into blocks optimized for parallel processing.

The VISC RISC-V processors purportedly deliver up to 100x efficiency in algorithms typically used in AI and machine learning and other highly complex math operations like cryptography and codecs. It relies on a single-issue multi-execute architecture and memory-efficient 64 x 128 deep byte-accessible registers to reduce power consumption. The system breaks algorithms into smaller parts that can be executed in parallel without synchronization issues that often occur in parallel processing. By doing so, large computations can take considerably less time and use less power.

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