TSMC Certifies a Host of Top EDA Tools for New Process Nodes

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With TSMC scaling down to 2 nm and lower, the semiconductor giant is working with Cadence, Siemens, and Synopsys to bring updated EDA tools to IC designers.

www.allaboutcircuits.com/, May. 08, 2024 – 

Taiwan Semiconductor Manufacturing Company (TSMC) is recognized as the world leader in semiconductor fabrication. Though the company is working with top EDA companies to certify their IC design tools for its 2 nm process technology, TSMC has already set its sights on 1.6 nm chips in the near future.

Chip designers must have electronic design automation (EDA) tools to develop integrated circuits for these new nodes. To this end, some of the industry's most prominent EDA companies, Synopsys, Cadence, and Siemens, each recently announced collaborations with TSMC to add support for TSMC's latest nodes to their EDA tool suite.

Cadence: A Push for 3D ICs, Advanced Nodes, and Photonics

Cadence and TSMC recently announced a collaborative effort to optimize Cadence's tool suite for TSMC's 2-nm process technologies.

These optimizations cover a range of applications, from digital and analog design flows to semiconductor power integrity analysis. Cadence's Innovus Implementation System and Genus Synthesis Solution are now certified for TSMC's N2 design flows, and the Cadence Integrity 3D-IC platform now features enhanced capabilities for handling complex multi-chip designs using TSMC's 3DFabric technologies.

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