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Sigasi Redefines Chip Design Creation, Integration, Validation Leveraging Shift-Left Principles

Jun. 07, 2024 – 

GENTBRUGGE, BELGIUM –– June 6, 2024 –– Sigasi®, the company redefining hardware description language (HDL) creation, integration, and validation for chip design, today rolled out a comprehensive portfolio developed to catch specification errors early in the chip design cycle and fix the inefficient HDL-based design flow.

It will present the new Sigasi Visual HDL™ (SVH™) portfolio supporting the shift-left methodology for chip design during the 61st Design Automation Conference (DAC) in San Francisco in June.

“Shifting left prevents costly mistakes and makes hardware design and verification more efficient, an improvement over the traditional HDL-based design flow that is no longer viable,” states Dieter Therssen, Sigasi’s CEO. “Sigasi’s new product portfolio gives hardware designers and verification engineers the workflow makeover they need, enabling them to work in a powerful environment to create, integrate, and validate their designs while leveraging shift-left principles.”

Introducing Sigasi Visual HDL

The traditional HDL workflow cannot accommodate the massive amounts of design specifications from generative artificial intelligence (genAI) creations, high-level synthesis results, and other complex system-on-chip (SoC) intellectual property (IP). These new levels of abstraction need to plug and play alongside large HDL files containing functionality created with domain-specific knowledge in order to integrate hundreds of billions of transistors on a chip. The Sigasi Visual HDL portfolio is an integrated development environment (IDE) able to take advantage of the shift-left methodology and give hardware designers and verification engineers better insight during the design progress.

SVH enables hardware designers and verification engineers to easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. It does so by standardizing the concept of an HDL design project. This is a shift left of simulation and synthesis projects, into a world of integrated development, synchronous visualization, and shift-left validation.

Integrated Development: SVH is fully integrated with Microsoft’s Visual Studio Code (VS Code), the most popular IDE, according to Stack Overflow's 2019 survey, with a rich marketplace of productivity tools. It includes sophisticated applications to easily use git and GitHub Source Control Management, as well as a selection of utilities to facilitate mundane tasks like extracting TODO comments or bookmarking important sections in HDL code.

Synchronous Visualization: SVH lets users move seamlessly through hierarchy views and graphics that update instantaneously as they make changes in their code.

Shift-Left Validation: SVH flags problems while users enter HDL code. Starting with syntax and semantics, it enforces coding styles as recommended by safety standards such as DO-254 or ISO 26262 and catches UVM abuses.

SVH comprises a tiered portfolio, offering three commercial editions meant to meet specific SoC design and verification challenges and seamless integration with an AI engine. This translates into greater reliability and productivity than traditional HDL editors. Each tier offers a comprehensive package of features, including type-time syntax and semantic checks and guardrails that enforce coding styles, policies, and standards. Regardless of which tier they use engineers receive instant feedback and warnings for all files associated with a project.

  1. Designer Edition meets the specific needs of individual engineers who need introspection of their HDL projects. It includes all the essential guidelines and tools to create quality code: from hovers and autocompletes to quick fixes, formatting, and rename refactoring.
  2. Professional Edition builds on the Designer Edition to incorporate more complex features focused on verifying HDL specifications. These include graphic features like block diagram and state machine views, and UVM support.
  3. Enterprise Edition offers features needed by large engineering teams, including command-line interface capabilities to safeguard the code repository and ensure better handoff to verification groups. It also includes documentation generation, all part of a better HDL hand-off.

Additionally, Sigasi offers a fully functional Community Edition that lets users explore its features for non-commercial uses. This is also an excellent tool for students and teachers to use to better learn the fundamentals of HDL design. Indeed, the capabilities and frictionless access offered by the Community Edition means that students need no longer request a limited-time educational license: they can download the VS Code extension and upgrade their HDL education. Professors who want to use Sigasi at scale in their classes can get in touch to discuss educational partnerships with the company.

Availability and Pricing

The Sigasi Visual HDL portfolio will be available at the end of June. Pricing is available upon request.

More details can be found on the Sigasi website or by emailing sales@sigasi.com

At 61st Design Automation Conference (DAC)

Sigasi will fly its new logo and tagline “Put Your Semicolons to Work” while exhibiting its Sigasi Visual HDL at DAC Booth #2416 (second floor). DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

To arrange a meeting to talk about what Sigasi Visual HDL portfolio can do for your company, send an e-mail to: dacmeeting@sigasi.com.

DAC registration is open.

About Sigasi

Sigasi’s driving force is the shift-left principle: instilling the importance of catching potential errors and issues in specifications at the front-end of the design cycle, preventing costly mistakes and making hardware design more efficient from the start., The company seeks to pioneer a new era of chip development, prioritizing user experience and design integrity, empowering hardware designers and verification engineers to achieve excellence in HDL creation, integration, and validation. Founded in 2008, it is privately held and self-funded.


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