Multi-Die Health and Reliability: Synopsys and TSMC Showcase UCIe Advances

synopsys.com, Jan. 09, 2025 – 

Although multi-die designs – an increasingly popular approach for integrating heterogeneous and homogenous dies into a single package – help resolve problems related to chip manufacturing and yield, they introduce a host of complexities and variables that must be addressed. In particular, designers must work diligently to ensure the health and reliability of their multi-die chip throughout its lifecycle. This includes testing and analysis of not only each individual die, but also die-to-die connectivity and the entire multi-die package.

Synopsys is at the forefront of multi-die design innovation, and we recently worked with TSMC to demonstrate two dies communicating via the high-speed UCIe (Universal Chiplet Interconnect Express) specification. Synopsys Monitoring, Test & Repair (MTR) IP was central to the demonstration, showing manufacturing and in-field health of the multi-die interconnect.

Read on as we explore the unique challenges of ensuring multi-die quality and reliability, why a comprehensive monitoring, test, and repair solution is crucial for chip designers, and what Synopsys and TSMC are doing to help.

The need for interconnect monitoring, test, and repair

As semiconductors become more complex – with multiple heterogeneous and homogeneous dies integrated into a single package – the need for effective communication and reliable interconnects between the dies (also called chiplets) has greatly increased. The UCIe specification has standardized die-to-die interconnects and facilitates high-speed communication between chiplets. However, the high-speed nature of these connections necessitates rigorous monitoring, testing, and repair to ensure seamless communication over the lifecycle of the chip. Monitoring signal integrity is vital for ensuring the overall health of interconnects. Rigorous algorithmic-based testing can uncover different types of opens, short, and crosstalk between interconnects that can manifest in these high-data-rate lanes in proximity. Equally important is the ability to cumulatively augment any repair signature across Process, Voltage, and Temperature (PVT) corners to cover different use cases...

Click here to learn more...

 Back