D&R News Alert
www.design-reuse-embedded.com
www.design-reuse.com
www.design-reuse-china.com
February 22nd, 2024
In this issue
• Arm CSA and AMBA release provide boost for chiplet ecosystem
• Intel Launches World’s First Systems Foundry Designed for the AI Era
• CEA-Leti Develops Novel Architecture for Keyword-Spotting (KWS) In Always-On, Voice-Activated Edge-AI Systems
$var->USER_FIRSTNAME

Welcome to the issue of February 22nd, 2024 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Foundry Ecosystem
Design Platforms
Design Centers
Synopsys
Silicon Lifecycle Management (SLM) Path Margin Monitor IP:
• Create timing margin heat map for functional paths in an SoC
• Achieve better PPA by leveraging silicon model calibration
• Provides key input for AVFS/AVS based optimization schemes

READ MORE >>    

Chiplets
Analog
Interface
High Performance Audio IP Cores in 22nm
• Bluetooth RF IP
• LC3+ Audio Codec
• USB 3.0 Phy / Controller IP

Memory IP
RISC-V
Article
 ❖ Leveraging the RISC-V Efficient Trace (E-Trace) standard

Quantum Computing
Artificial Intelligence
Security
Products
 ❖ Xiphera XIP4200H - ECC Accelerator

Wireless
Products
 ❖ Sirius Wireless Low Power BTDM5.3 Connectivity Transceiver
❖ Singmai PT8 - Broadcast quality video encoder for all NTSC and PAL video standards

In the FPGA World
Products
 ❖ NanoXplore NG-Ultra - Radiation Hardened FPGA

Green Electronics
Partner News
Blog
 ❖ 2024 Outlook with Laura Long of Axiomise

Business News
Do not miss IP SoC
Silicon Valley 2024
When: April 25th, 2024 		Last Chance to Submit
your contribution >>
Registration Open >>







Secure-IC
Post-Quantum Cryptography IP: Crystals Kyber - Crystals Dilithium - XMSS - LMS

What they said at
IP SoC Conference 23

Transforming Far-Edge Computer Vision with Energy-Efficient A
Vincent Huard, Chief Technology Officer, Dolphin Design

IP Core Considerations for Ensuring Functional Safety in Safety-Critical Applications
Philipp Jacobsohn, Senior Staff Applications Engineer, SmartDV Technologies

GRLIB: VHDL IP library for fault-tolerant SoC
Fabio Malatesta, Product Marketing Engineer, Frontgrade Gaisler

CAN XL - can safety go in hand with performance?
Jacek Hanke, CEO, Digital Core Design

Solve the Latest ISO 21434 Cybersecurity Challenge with an Automotive HSM
Ruud Derwig, Senior Staff Engineer for Security IP, Synopsys, Inc.

Which IP for Which Security Certification Standard,
Ludovic Merrien, Security Certification Leader, Tiempo Secure

LDPC Encoder/Decoder
Manish Mahajan, Founder, Secantec, Inc.

Security from chip to cloud with PQC (Post-Quantum Cryptography)
Brice Gaignoux, EMEA Pre-Sales Engineer, Secure-IC

A novel approach for SoC design resource management and prediction
Chouki Aktouf, Co-Founder, Innova Advanced Technologies

Multi-IO co-processor with TSN
Vincent Laporte, CTO - V.P. BU, CetraC

REGISTER:
If this newsletter was forwarded to you by a colleague, you can have it sent directly to you at no cost. To register for D&R SoC News Alert, go to: https://www.design-reuse.com/users/signup.php

UPDATE YOUR PROFILE / UNSUBSCRIBE :
You are subscribed as $var->USER_MAIL and you receive this Alert in html format.

* If you wish to unsubscribe, you can do it there:
https://www.design-reuse.com/users/alert.php?u=$var->USER_ID&e=$var->USER_MAIL