CEVA-BX2 is a multipurpose hybrid DSP and Controller, designed for the inherent low power requirements of DSP kernels with high-level programming and compact code size requirements of a large control code base.

The CEVA-BX2 addresses intensive workloads such as 5G PHY control, multi-microphone beamforming, AI processing and neural networks for speech recognition, with up to 16 GMACs per second.

CEVA-BX2 uses quad 32X32-bit MACs and octal 16X16-bit MACs, with enhanced capability for supporting 16x8-bit and 8x8-bit MAC operations.

The CEVA-BX2 is using an 11-stage pipeline and 5-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz at a TSMC 7nm process node using common standard cells and memory compilers.

The CEVA-BX2 Instruction Set Architecture (ISA) incorporates support for Single Instruction Multiple Data (SIMD) as well as optional floating point units for high accuracy algorithms.

The CEVA-BX2 is accompanied by a comprehensive software development tool chain, including:

• Advanced LLVM compiler


• Eclipse based debugger


• DSP and neural network compute libraries


• Neural network frameworks support


• Real Time Operating Systems (RTOS)