The modular architecture of the Tyr family is well suited to meet the challenges of autonomous driving. With a computational power of 1,032 TeraFLOPS, the Tyr3 processes an eight-million cell particle filter using 16-million particles in less than 5 milliseconds (msec). A full-high-definition (FHD) image with Yolo-v3 takes less than 1.6 msec leading to a throughput of 625 images per second.

The Tyr family is implemented using VSORA s proprietary low-power architecture to achieve more than 80% usage efficiency approximating the theoretical maximum processing power, eliminating the need for expensive multi-chip or hardware accelerator solutions or special cooling solutions.

Tyr, a family of three different chips called Tyr1, Tyr2 and Tyr3, offers a fully programmable architecture that tightly couples digital signal processing (DSP) cores with machine learning (ML) accelerators necessary to design L3 through L5 autonomous driving vehicles. The Tyr companion chip is algorithm and host processor agnostic and can be integrated into new or existing environments without the need to redesign the entire system.