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M-PHY is a high-speed serial physical interface technology with flexible signal characteristics and high bandwidth capabilities, which is particularly developed for mobile applications that offer increased performance, effective power management schemes, robustness against RF interferences and low RF emission to obtain low pin count combined with very good power efficiency.

MPHY module is basically worked on the principle of master and slave, where M-TX is served as a Transmitter and M-RX is served as a Receiver. Designed with the different power modes MPHY provides the benefit of low power consumption and with the number of lanes it adds greater bandwidth for data transfer.

It is targeted to be suitable for multiple protocols: * DigRFv4, UniPro, LLI, CSI-3 and DSI-2 protocol interconnect standards of the MIPI Alliance * UFS, eMMC, etc. Memory protocol standards of JEDEC and USB-IF respectively

Product details

  • Provide greater flexibility to the design by using RMMI interfaces which gives liberty to the designer to integrate it with the various MIPI protocols such as CSI3 ,DSI2, LLI ,DIGRF V4.0 ,UFS controller etc.
  • Our design includes DIF-P and DIF-N signalling interfaces for the communication between M-TX and M-RX.
  • It supports both High speed and low speed signalling for data transfer for both TYPE-1 and TYPE-2 module. Both M-TX and M-RX has implemented in such a way so it can support all the Different power modes, all the GEAR (HSG1-G3 and PWMG1-G5).
  • To make the MPHY IP more robust we have also implemented the optional 8b/10b encoder and decoder which provides the error checking facilities.


  • High Level Synthesizable (HLS) SystemC models.
  • High quality M-PHY RTL
  • Supports RMMI interfaces
  • 8b/10b encoder decoder for error checking.
  • Implementation of power modes to achieve greater power efficiency.
  • Supports TYPE-1 module (can be configured with TYPE-2).
  • Gears implementation to achieve maximum speed 5.8 GB/lane.
  • Support for both high speed and low speed mode
  • Supports multiple transmission speed ranges (PWM G0-G7, all HS-GEARs (HSG1, HSG2 and HSG3)).
  • Integrated SystemC-UVM Verification setup.


  • High Level Synthesizable (HLS) models
  • RTL
  • UVM Verification setup
  • Documents
    • Product Specification doc
    • User guide
    • Reports
    • Checklist
    • Test cases
  • Technical Support

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