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Tessent Status Monitor


The Tessent Embedded Analytics Status Monitor provides visibility and monitoring of any circuitry within a System-on-Chip (SoC). It affords many of the benefits of a logic analyzer, but with no need to bring signals off-chip.

The Status Monitor provides a wide variety of functions including debugging, reporting diagnostics, and performance profiling. It can be parameterized at instantiation to precisely monitor the logic signals within the host SoC that interest the engineering team, giving visibility of those internal signal lines that would otherwise be inaccessible once the SoC is delivered, as well as during FPGA prototyping or emulation.

All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.

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