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LPDDR4 DRAM Memory Model is implemented as per JEDEC standard JESD209-4A and provides an effective & efficient way to verify the LPDDR4 components of an ASIC/FPGA system. It is a part of Arastu s comprehensive low power verification suite which also includes LPDDR4 DFI PHY Functional Model and LPDDR4 DRAM Bus Monitor.


  • Support for LPDDR4 memory devices from all leading vendors
  • Supports multiple device densities: 4Gb to 32Gb
  • Supports capturing of all the valid LPDDR4 commands as per the JESD209-4A specifications
  • Supports programmable READ/WRITE latency and related timings
  • Supports all Power Down modes
  • Supports Mode Register (MR) programming
  • Supports callback for all Mode Register read/write, Memory read/write which generates any scenario for verification and custom use
  • Reports all timing violations and protocol rule checks
  • Supports Target Row Refresh (TRR) and Post Package Repair (PPR)
  • Clock Stop and Dynamic frequency change to any valid DDR operating frequency
  • Developed using SystemC to facilitate seamless integration in any verification environment

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