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EJTAG probe featuring iFlowtrace trace system for MIPS32, M14K, M14Kc, and M4K cores and microcontrollers. The Navigator iFlowtrace probe consists of the Navigator EJTAG probe with instruction trace support for MIPS-based cores that are enabled with iFlowtrace (Instruction Flow Trace). iFlowtrace technology is an option on the MIPS32M14K and M4K cores that allows tracing of all executed MIPS32 and microMIPS instructions, while minimizing on-chip resources and pin requirements - especially critical for microcontroller designs. A high degree of compression is used to reduce bandwidth to capture all program execution flow and maintain high throughput. The iFlowtrace physical trace port has one double data rate (DDR) clock and four data lines. The Navigator iFlowtrace probe has a single connector on the probe end and a split cable on the target end with two connectors - the standard 14-pin EJTAG connector and a 10-pin iFlowtrace connector. The EJTAG connector is plugged into the standard dual-row 14-pin header on the user s target board, providing complete run control of the M14K and M4K cores. The iFlowtrace connector connects to a matching 5 x 2 pin header on the user s target board that carries the clock and four data trace signals to the probe. Extensive debugger support includes MIPS Navigator Console Software and the Eclipse-based MIPS Navigator ICS on Windows and Linux The MIPS Navigator Console Software is a tcl-based command console that provides full control of a target using the Navigator iFlowtrace Probe. Software development tools used with the Navigator probe also includes the GNU-based MIPS toolchain and the MIPS Navigator Integrated Component Suite (ICS). All probe features are available from the Navigator ICS interface, which has an Eclipse-standard interface and C/C++ Development Tool (CDT) components with special plug-ins for processor debugging using the probe. The system runs on a PC with Windows XP or Windows 7 or Linux and requires a USB 2.0 or 10/100 Ethernet connection.


  • Supporting microAptiv, interAptiv, proAptiv and Series5 cores
  • Supports all MIPS32 processor designs, leveraging the off-chip trace features available in the core
  • Supports multiple source level debuggers including the CodeSourcery embedded C/C++ toolchain, MIPS Navigator ICS, and GDB
  • Supports on-chip and off-chip capture modes depending on processor implementation
  • Real-time PC execution trace, load/store address, and data trace
  • Trace can be gated on/off by on-chip triggers
  • Scalable internal trace depth or external trace port width and speed
  • Trace depth up to 2GB in external trace mode
  • Unlimited software breakpoints via SDBBP instruction
  • Single-step by assembly or C source line
  • Read-write all CPU registers
  • Read-write memory whether CPU is stopped or running
  • MIPS-standard hardware breakpoints
  • Flash programming support
  • Multi-core debug with multiple MIPS cores
  • Mixed core debug with MIPS and other cores supported as an option
  • Go, halt processor run control
  • Low-level access to JTAG functions for silicon verification
  • Single line assembler and disassembler
  • Command-line interface with Tcl/tk scripting language standard
  • Binary software interface adheres to MDI specification
  • Supports virtualization features available in certain cores to view current guestID, view/modify guest CP0 registers, access guest memory, and view or modify the root and guest TLB entries
  • Supports virtualization triggers and trace; qualify triggers on a guestID, qualify trace for a specific guest, trace transitions between guests and record the guestID

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