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Overview

Gate-Level X-Verification : Reduce Bring-up Time

Block Diagram

Features

  • Adressing X-pessimism in GLS is a must
    • Formal-enhanced logic simulation dynamically performs X-pessimism analysis and repair on the fly
    • Analyzes X propagation in datapath and gated clock logic
    • False X fixes reusable on subsequent simulation runs
    • Supports hierarchical flow for large designs
  • Eliminate race conditions in 0-delay GLS
    • 0-delay GLS may demonstrate race conditions especially in designs with gated clocking and delay lines
    • pseudo-SDF generator efficiently solves race conditions issues
  • Detect simulation glitches
    • Dynamic glitch detectors uncover hard to find X corruption cases (0->X->1)
  • Uncover testbench forcing and connectivity issues in GLS
    • Formal-enhanced logic simulation dynamically performs X-pessimism analysis and repair on the fly
    • Force/release propagation analysis confirms when forces no longer drive any fanout due to synthesis optimizations
    • Connectivity analysis finds modules with undriven inputs creaing X sources
  • Compements other simulator-based X prop tools
  • Effectively root cause the source of real X s
    • Smartlog shows X agressors and their sequential timesteps
    • Finds dynamic corruption of DFFs
    • Supports RTL, TRL/gae, and gate-level designs
    • Supports Simvision, Verdi, and Questa Wave

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