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All Verification IP

Overview

Accelerate RTL Verification and SW Bring-up Target IPs and SoCs
  • NVMe controller
  • PCIe RC/EP IP, Repeater, Switch
  • Flash controller
  • AMBA NoCs and peripherals
  • More AVIPs planned ...

Block Diagram

Features

  • TRL simulation accelerator targets >100-1000X speedups over simulation
  • Seamless support of simulation and accelerated VIPs
  • Full line of Accelerated VIPs (AVIP) built using high quality, proven, commercial-grade design IPs including PCIe, NVMe, AMBA AXI4/AHB/APB, DDR4/LPDDR4, ONFI Flash
  • Integrated HW-SW co-verification using AMBA VIP/AVIP virtual prototype (VP) adapter supporting ARM, RISC-V, and MIPs VPs including ARM Fast Models and Imperas OVPs
  • Unified HW-SW co-debug using/SW/HW breakpointing and data structure inspection
  • Multi-FPGA design partitioner targets multi-FPGA board solutions up to 16 FPGAs
  • Enhanced FPGA debug visibility via Monitor AVIP supports protocol-aware debug, tracker logs, and waveforms
  • Assertions-based verification via optimized replay of accelerator traces on RTL assertions
  • Utilizes commercial and customer FPGA prototype boards, Xilinx ® FPGAs and tools, and other 3rd party FPGA debug tools
  • Low cost alternative by fully leveraging same investment in FPGA prototype systems, design process and tools, and engineering resources
  • Comprehensive verification services to partition DUT into multiple FPGAs, integrate with SIP/AVIP/VP IPs, implement FPGAs, and run verification on DUT

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