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Gate-Level Parallel Simulation : Reduce Time to Simulation Sign-off

Block Diagram


  • Run post-layout, SDF-based gate-klevel simulation using multi-core and multiple server clusers
  • Speed up simulations by 3-5X
  • No design changes, no testbench changes, no SDF changes
  • Engines run cycle-based or lock-step synchronization
  • Supports all three major simulators (Xcelium/VCS/Questa)
  • Simulation analyzer tool generates design blocks workload, port change activities, interconnect complexity between blocks, synchronization analysis, and design hierarchy report
  • Automatic coarse-gained partitioning of flat and hierarchical netlists
  • Patent pending methods further optimize performance

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