SOC Design

When developing new System on Chip (SoC) devices our experienced design teams can deliver turn-key design solutions.

Customers can work with EnSilica to support their own product development teams by providing access to expert advice on all aspects of the SoC development process from architectural design and specification to final chip production, test and yield management.

• Chip Specification

  Our SoC specification development services start with our customer high level marketing specification to finish with a complete system architecture and set of detailed technical specifications from the top-level to individual modules. The process involves exploration of architectural alternatives as well as analog/digital, hardware/software and cost/performance design decisions.
  

• Digital Design

  EnSilica maintains an experienced in-house design team with a wide variety of specialized skills and expertise using the latest design methodologies and tools from Cadence, Mentor, Synopsis and others.

• Analog / Mixed Signal Design

Our expert AMS engineers can specify, develop, test, integrate, deliver and support all aspects of an analog design, including integrating select 3rd party IPs or creating custom low power as well as high speed analog designs.

• RF Design

  EnSilica offers RF design, development, production, test, and qualification services. Our expertise spans from high frequency (HF) to Ka-Band frequencies and includes RF components such as: transceivers, transmitters, and receivers and as well as RF subsystems: upconverters, downconverters, front ends, low noamplifiers, power amplifiers, bidirectional amplifiers and RF filters.

FPGA System Level Design

Modern FPGA based systems have expanded in complexity.

EnSilica are skilled in working with customer marketing and engineering teams to define new features that help differentiate your product in the market through the use of FPGAs. EnSilica can assist or take ownership of all aspects of the system-level FPGA design. Whether the requirement is for a feasibility study, algorithm analysis, we have the expertise to solve the most difficult design problems. We have experience with the latest high level design methodologies reducing the time to market through the use of OpenCL, Altera DSPBuilder or Xilinx Systems Generator for DSP. For us innovation and proven technology can go hand in hand to both differentiate and lower risk at the same time.

• SoC Architecture

  New digital designs invariably are a mix of software, hardware and peripherals. When it comes to software the designer has a wide choice of processor cores, some of which are technology specific, some hard, others soft, and some offering different levels of configurability to improve the requirements fit. This daunting variety is often tempered by the availability of a good toolchain and on-chip debug.

• RF Systems Analysis

  The RF front end of a typical communications receiver is a complex design. The System Engineer has an overview of how the AGC, frequency, phase and analog impairment correction loop should operate, spanning the RF and digital signal processing. It is quite often the case that digital calibration can compensate for analog impairments, leading to a lower cost receiver chain, or that digital gain can be substituted for analog gain without the SNR falling below the demodulation threshold. A full analysis of receiver sensitivity and noise figure can only be carried out with knowledge of the RF and DSP performance.

• DSP Alogorithms

  The use of DSP is all pervasive yet for many engineers DSP is still a black art and this forces them to consider well documented solutions. One such example may be to choose a simple FIR filter because the design tools for these are commonly available. There can be instances where different filter architectures present lower cost, latency or higher performance whilst still meeting the original requirements. This knowledge and optimization is not restricted to simple filters but extends to all areas of digital signal processing.
  

  ASIC Development Services

  
  Advances in ASIC technology continue to open up new opportunities but they also present new challenges:
  
  • Increasing design complexity and timescale pressure
  • Advances in silicon process capability
  • Performance, cost, and power optimisation
  • Verification complexity and coverage
  • IP selection and integration
  • New EDA tools and methodologies

  EnSilica s engineers live and breathe these ASIC Development challenges every day. Our experienced silicon team can deliver a complete turn-key ASIC design, or provide specialist consultants who can work with your engineering team to help deliver your ASIC project on-time and in the most cost-effective way and can offer the following ASIC development services.

  • RTL Coding

    High quality HDL code ensures good quality of results from synthesis and facilitates efficient reuse. EnSilica has extensive experience in creating a broad range of designs using both Verilog and VHDL, based upon a robust set of coding guidelines.

  • Functional Verification

    The ability to develop a high quality verification strategy is one of the key activities that will determine the success of your ASIC project. Get it wrong and you are looking at a silicon re-spin with typically a 6 months delay in getting your product to market with substantial cost and revenue implications.

    EnSilica can help identify the right verification strategy for your design, one that will provide high confidence that the functional requirements defined in the specification are indeed implemented correctly. Learn more about our Advanced ASIC Verification services.

    EnSilica are members of the Mentor Graphics Questa Vanguard Program (QVP) and Cadence Verification Alliance Program.

  • Logical Implementation

    EnSilica have the expertise needed to support the logical implementation of your design, including synthesis, DFT/ATPG/MBIST, STA, and Logical Equivalence. We can then interface with your chosen layout team, whether this be EnSilica, your own team, or a 3rd party layout company, to help make sure you get optimum results at the physical implementation stage.

  • Physical Design

    EnSilica can support the physical design of your chip from netlist all the way through to generation of GDSII ready for foundry tapeout. Physical design includes floorplanning, clock-tree synthesis, place-and-route, timing closure, power optimisation, and sign-off verification. Benefiting from detailed knowledge gained through the logical implementation and verification activities,