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You are here : design-reuse-embedded.com > Design Partners > Design Services

Pacific Microchip Corp. - ASIC/IC Design Services

Overview

Pacific Microchip is an ASIC/IC design services provider. Incorporated in 2006, Pacific Microchip offers a wide range of ASIC design expertise: SERDES, Modulator Drivers, ADC, DAC, TIA and digital cores. We design and integrate on a single chip: analog, RF, mixed signal and digital functions. Our IP portfolio includes blocks for application in SERDES and transceivers. Previously used foundries: TSMC, GF, IBM, TowerJazz Semiconductor; the technology nodes include 28nm-350nm CMOS and 130nm/180nm SiGe. Our services include specification-to-silicon as well as assistance in any IC design stage.

Benefits

DESIGN complete Digital/Analog/RF/Mixed signal ASICs from spec to silicon.
ASSIST at any step of IC design, integration, characterization.
INTEGRATE Analog and digital blocks provided by customer or third party.
DELIVER IP blocks ready for integration.
PROVIDE on-site or off-site assistance and support.

Zone	North America
Country	USA
Vendor Type	Design Services
Main Core Competency	Logic and High level Design , Physical Design

Features

Digital

Digital Design

Full backend cycle from RTL to GDS
Full-custom/Semi-custom RTL design
Test bench preparation
Hardware description languages: VHDL, Verilog
Layout floorplanning, partitioning
Place-route and optimization
Clock tree synthesis optimization
Detail timing analysis
Location aware on-chip variation analysis
Layout area minimization
Crosstalk/noise analysis and mitigation
Parasitic extraction, back annotation
Digital content integration within analog flow and vice versa
Support in design/verification tools setup
LVS/DRC rule deck customization
Custom components and Cells design
TCL, PERL and other script languages based design automation

Design

RTL Coding
Functional Verification / Simulation
Logical Synthesis
Physical implementation
Design Planning
Clock-tree synthesis
Placement and routing
RC Extraction
Design rules checking... and more

Design Porting

Migration to other processes/nodes
Migration to other design platforms
Full migration: re-synthesis and layouts
Semi-automated migration

Layout Design

Physical design

Full-custom/Semi-custom layout design
Full cycle from schematic to GDS
High-speed oriented design
Analog/precision oriented layout design
Layout area minimization
RCL parasitics aware layout optimization

Design Flow

Support in design/verification tools setup
LVS/DRC rule deck customization
Custom components and PCells design
Cadence SKILL based design automation
Reliable/efficient off-site design space integration with customer’s design space, and more

IP Portfolio

Silicon IP

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