www.design-reuse-embedded.com
SEARCH IP   
    • Categories
    • RISC-V
    • Embedded Processing
    • 5G, 3GPP LTE IP
    • IoT IP
    • Artificial Intelligence IP
    • Automotive IP
    • Space and Avionics
    • Security IP
    • Audio & Video IP
    • Design Platforms
    • Monitoring and Verification
    • SoC Design Services
    • Find your best SoC design partner
Partner Videos D&R Events
    • IP-SoC Days 2024
    • IP-SoC Days 2023
    • IP-SoC Days 2022
    • IP-SoC Days 2021
    • IP-SoC Days 2020
    • IP-SoC 2023
    • IP-SoC 2022
    • IP-SoC 2021
    • IP-SoC 2020
NEWS
Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...
You are here : design-reuse-embedded.com  > Design Partners  > Design Services
       

Overview

Silvaco offers fast-turnaround and affordable services for TCAD, SPICE Modeling, and PDK development.

PDK Development Services

EDA Tools in Custom IC Design Services


  • Gateway Schematic Editor

  • SmartSpice Circuit Simulator

  • Expert Layout Editor

  • Smart/DRC/LVS/LPE

  • Hipex Full-chip Parasitic Extraction

  • JavaScript/Lisa Scripting Language
Zone North America
Country USA
Vendor Type Design Services
Main Core Competency Logic and High level Design , Physical Design
Application Domain Automotive and Avionics , Internet of Things
Experience in Advanced Technology Nodes on Samsung

Features

Deliverables
  • Schematic Symbols – for the Gateway Schematic Editor to invoke Parameterized Cells in the Expert Layout design tool that are DRC and LVS correct. These parameterized symbols and respective subcircuits are integrated and tested with the SPICE models to assure a standard convention for transistor level simulation. PCells are written in the JavaScript/Lisa Scripting Language.

  • SPICE Models – SPICE model (optional) files, verified with the SmartSpice Circuit Simulator, at the foundry-supplied process corners (temperature, voltage, process). Silvaco will extract one set of models from a wafer or measured data and produce a complete measured vs. simulation report for each device.

  • Technology Files – layer files that correlate the legal GDSII layers for each of the process layers for layout and verification tools. Display files to customize the layout and schematic tools for GDS layers, display colors and user-customizable hot keys.

  • Rule Decks –contain the layout rules encoded into the format used by the Expert Layout Editor, Guardian DRC /LVS/LPE tools, and the Hipex Full-chip Parasitic Extractor.

  • Parameterized Cells – enable annotated device schematics to be automatically drawn in the Expert Layout Editor, DRC and LVS correct, using the LISA scripting language.

IP Portfolio

Silicon IP
SoC Solutions

Partner with us

Contact Us
Partnership Offers

List your Products

Suppliers, list and add your products for free.

List your Products

More about D&R Privacy Policy

© 2024 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.