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Marquee has a well-defined set of methodologies to deliver high quality work products in the following areas of digital design:

  • Microarchitecture
    • Functional Specification including consideration for System Level Performance/Power
    • Implementation Specification including Logical/Physical Level Partitioning for Optimum Physical Implementation

  • RTL Design
    • RTL Source Codes subjected to UPF Development Flow for Low Power Implementation
    • Comprehensive Reports with 0 Errors/Warnings
      • Lint
      • Clock Domain Crossing (CDC)
      • Reset Domain Crossing (RDC)
    • SDC File for Synthesis and Static Timing Analysis (STA)
    • Logical Equivalence Check (LEC) Report between RTL and Netlist

  • Design Verification
    • Multiple Verification Strategies
      • Directed Testing
      • Constrained Random Verification
      • Property Check using Formal Verification (FV)
    • Detailed Test Plan indicating the Verification Strategy, Test Items, Test Algorithm, and Functional Coverage Information
    • UVM-Compliant Test Environment and Source Codes
    • UVM-Compliant Test Environment and Source Codes
    • UVM-Compliant Test Environment and Source Codes
    • 100% Functional and RTL Coverage

  • Design for Test (DFT)
    • Chip and Unit Level DFT Architecture
    • Multiple Verification Strategies
    • Automatic Test Pattern Generation (ATPG)
    • Memory Built-In Self-Test (MBIST)
    • Logic Built-In Self-Test (LBIST)
    • Boundary Scan
    • At least 90% Fault Coverage

  • Physical Design (PD)
    • Complete RTL to GDSII Flow that meets the required Performance, Power, Timing, and Area
    • Design Rule Check (DRC) and Layout Versus Schematic (LVS) Clean Designs
    • Close Coordination with Analog Layout for Chip Signoff
Country India , USA
Vendor Type Turnkey Solution Provider

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