The Synopsys ARC® EM5D and EM7D processors are optimized for use in low-power embedded applications where DSP performance and low-power consumption are requirements.

The EM5D and EM7D processors are based on the ARCv2DSP Instruction Set Architecture (ISA), which adds over 150 optimized DSP instructions to the area- and code-efficient real-time ARCv2 RISC ISA. The EM5D and EM7D cores feature a power-efficient unified 32x32 MUL/MAC unit and support for fixed-point DSP data types and vector/SIMD (single instruction multiple data) operations. The EM DSP processors are configurable, enabling each instance of the core to be tailored to suit its specific application or DSP workload. For example the data path width can be selected and support for rounding, complex, divide and square root can be enabled or disabled.

The ARC EM DSP family features a balanced 3-stage Harvard architecture pipeline that provides efficient throughput and the cores offer excellent real-time control and DSP performance within a footprint as small as 0.03 mm2.

To enable easy DSP software development, the ARC MetaWare Development Toolkit features a rich DSP software library and the included enhanced C/C++ Compiler supports all of the new DSP functionality and offers industry-leading code density.