The Synopsys ARC® EM9D and EM11D processors are optimized for DSP-intensive functions such as sensor fusion, voice detection, speech recognition and audio processing that are common in Internet of Things (IoT) and other embedded applications. Typical "always-on" applications such as those in the IoT market need low power consumption, optimum device performance and extended battery life.

The ARC EM9D and EM11D processors are based on the ARCv2DSP Instruction Set Architecture (ISA), which adds over 150 optimized DSP instructions to the area- and code-efficient real-time ARCv2 RISC ISA. The EM9D and EM11D cores feature a power-efficient unified 32x32 MUL/MAC unit and support for fixed-point DSP data types and vector/SIMD (single instruction multiple data) operations.

These processors improve DSP performance by up to 3X and more adding multi-banked (XY) memories architected to alleviate DSP applications' need for fast memory accesses while performing repeated mathematical operations on arrays of numbers. The XY memory system consists of memory banks, address pointers, address update registers and address generation units (AGUs) and supports multiple configuration options (logical partitions with data CCM) as well as interleaving or splitting one logical partition into two physical memories supporting even and odd logical words respectively. The address generation units provide additional addressing modes such as modulo, bit reverse and variable +/- linear offset. They make complex address calculations independently, removing a significant overhead from the CPU and ensuring efficient memory access without cycle penalties.

To facilitate rapid development of software for EM9D and EM11D, the ARC MetaWare Development Toolkit has been enhanced to offer full C/C++ programming support for the cores' DSP instructions and XY memory as well as a rich library of DSP functions.