The APS25 is a fully 32 bit high performance general purpose CPU capable of meeting the demands of most computing tasks. It is suitable for creating complex embedded systems with caches, co-processors and multiple cores. The APS25 is an enhanced version of the APS5 that utilizes the 2nd generation Cortus Instruction Set Architecture to provide improved code density with only a marginal increase in silicon area. The instructions are 16, 24 and 32 bits in length ensuring optimal code density. The 5-7 stage pipeline ensures ultra low power consumption and high performance while retaining a reasonable maximum clock frequency. Out-of-order completion enables nearly all instructions to execute in a single cycle, including loads and stores. Interrupts are fully vectored and the architecture ensures a minimum of software overhead in task switches.