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All Silicon IP


AndesCore™ NX25 is a 64-bit CPU IP core for applications with memory usage greater than 4G bytes, which is the bound of 32-bit processors. NX25 let high performance computing with very little silicon footprint achievable by its AndeStar™ V5m Instruction Set Architecture, which combines the latest RISC-V RV64IMAC technology with Andes™ research in performance enhancements, also with the manually fine-tuned design that let the core operates fast as over 1 GHz at 28nm process. Multiple functional options are available to tailor the implementation to best fit target product applications. There are system level supporting functions with enhance features such as vectored interrupt for RISC-V Platform-Level Interrupt Controller (PLIC), and exception redirection for Debug Module. Andes Technology s comprehensive infrastructures of development environment for AndesCore® NX25 such as platform design, toolchain framework and service network are also provided.


AndeStar® V5m Architecture
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
  • Enabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs
  • Andes exclusive performance and functionality enhancements
  • 16/32-bit mixable instruction format
  • For compact code density
  • Optimized between core size and performance requirements
  • Embedded systems with privilege protections

CPU Core
  • Superior performance-per-MHz
  • Superior performance-efficiency, while allowing for high speeds
  • Branch Target Buffer to speed up control codes
  • Branch History Table and Return Address Stack to speeds up procedure returns
  • Easily identifies stack size threshold during development
  • Hardwired stack overflow and underflow error detection during runtime
  • Option to choose between speed and area according to application requirements
Memory Subsystems
  • Higher performance for large program size
    • Accelerating accesses to slow memories
    • Flexible cache configurations
  • Higher efficiency for program execution
    • Flexible size selection to fit diversified needs
  • Code and data integrity protection
  • User-selectable bus interface for optimal efficiency
  • Efficient data transfer
  • Simplified SoC integration
  • Applications

    • Large-scale network controllers
    • High capacity storage devices
    • Data analytic accelerators
    • Computer Vision and Pattern Recognition
    • Artificial Intelligence to Deep Learning

    Block Diagram


    AndeStar® V5m Architecture
    • RISC-V RV64IMAC Instructions
    • 64-bit CPU architecture
    • Andes Extended Instructions
    • 16/32-bit mixable instruction format
    • For compact code density
    • 32 general-purpose registers
    • Machine (M) and User (U) Privilege levels
    CPU Core
    • 3.2 DMIPS/MHz 3.44 CoreMark/MHz
    • 5-stage pipeline, with a full-cycle reserved for critical SRAM accesses
    • Extensive Branch Predication features
    • Branch Target Buffer (BTB): 32, 64, 128 or 256-entry
    • Branch History Table (BHT): 256-entry, with 8-bit branch history
    • Return Address Stack (RAS): 4-entry
    • Hardware stack protection
    • Multiplier options
    • Fast multipliers: pipelined, 2-cycle
    • Small multiplier: producing 1, 2, 4, or 8 bits per cycle
    Memory Subsystems
    • I & D Cache
    • Size: 8KB to 64KB
    • Set associativity: Direct-mapped, 2-way or 4-way
    • ILM & DLM
    • Size: 4KB to 16M
    • Bus masters accesses by AHB slave port
    • I & D Cache, ILM & DLM soft-error protection: ECC or Parity
    • Master port: AHB or AXI with 64-bit data, 32 to 64-bit address
    • Save port: AHB with 64-bit data, for ILM/DLM accesses
    • N:1 core/bus clock ratios

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