The Trilinear Technologies M4 Digital Video Decoder is a hardware only implementation providing high quality and high performance h.264 video decoding. The M4 core supports the Constrained Baseline and Main Profiles as well as providing optional support for the High4:2:2 profile. All profiles are capable of decoding streams at the 4.2 level for FPGA implementations and the 5.1 level for ASIC implementations.
The host system communicates with the M4 core using the AMBA 3 APB slave interface. Control and status information provides real-time visibility of the core for applications requiring fine control of the decode process. For most applications, the core implements an autonomous mode where decoding proceeds without input from the host until a specified break point is reached.
The frame store is accessed through a direct high speed, wide bus, memory interface.Decoded picture storage can be configured based on the input video stream which allows the minimum amount of memory to be allocated for a specific stream. The memory system is tolerant of high latency which makes the M4 core ideal for implementation in a shared memory system.