www.design-reuse-embedded.com
SEARCH SOLUTIONS   
    • Categories
    • RISC-V
    • Embedded Processing
    • 5G, 3GPP LTE SoCs
    • IoT SoCs
    • Artificial Intelligence SoCs
    • Automotive SoCs
    • Space and Avionics
    • Security Solutions & SoCs
    • Audio & Video SoCs
    • Design Platforms
    • Monitoring and Verification
    • SoC Design Services
    • Find your best SoC design partner
Partner Videos D&R Events
    • IP-SoC Days 2024
    • IP-SoC Days 2023
    • IP-SoC Days 2022
    • IP-SoC Days 2021
    • IP-SoC Days 2020
    • IP-SoC 2023
    • IP-SoC 2022
    • IP-SoC 2021
    • IP-SoC 2020
On Demand Webinars NEWS
Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...
You are here : design-reuse-embedded.com  > Multi Media Vision  > Video Codec

DSC Decoder

Overview

Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has been also adopted into the VESA's eDP v1.4 and the MIPI DSI standard.

Compliant with the VESA DSC 1.2a standards, CYB-DSC2d IP core supports MMAP, BP, MPP, ICH and 4:4:4 sampling. It performs visually lossless compression, low gate count and latency for ultrahigh definition display applications. It can be fastly and easily integrated into ASIC and FPGA applications for 4K / UHD TV, DisplayPort 1.4, USB Type-C device and AR / VR product.

Partner with us

Contact Us
Partnership Offers

List your Products

Suppliers, list and add your products for free.

List your Products

More about D&R Privacy Policy

© 2024 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.