The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The NOEL-V is designed for space applications: with its high-performance and fault-tolerant design, NOEL-V is the ideal choice for satellites, rovers, and other space-bound systems. Built on the RISC-V architecture, NOEL-V offers unparalleled flexibility and customization, allowing SoC designers to create solutions tailored to their specific needs. Software developers have access to a vast library of existing software and tools to help them create the perfect solution.

The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, the NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable fast stores and fast cache refill.

The NOEL-V is interfaced using the AMBA 2.0 AHB bus (but a subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the GRLIB IP library. The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.

The cache memories of the NOEL-V processor are safeguarded from radiation-induced Single Event Upsets (SEUs) through a patent-protected error correction scheme. This scheme is capable of correcting single bit errors, detecting double bit errors, and even detecting 3-bit and 4-bit adjacent bit errors. The correction is implemented transparently in the cache controller without the need for software intervention or extra memory access.
Additionally, the caches include a hardware mechanism that can be activated to automatically scrub the memories, preventing error accumulation. The fault tolerance features can be activated in all the NOEL-V configurations.