XIP3026B from Xiphera is a balanced Intellectual Property (IP) core implementing the secure hash algorithms SHA512, SHA384, SHA512/216 and SHA512/224 as specified in the Secure Hash Standard published by the National Institute of Standards and Technology (NIST). The message is parsed and padded into 1024 bits long message blocks, and the resulting message digest (hash value) is either 512, 384, 256 or 224 bits long.

XIP3026B has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3026B does not rely on any FPGA manufacturer-specific features.