SphinX is designed to accommodate the speed, latency and throughput requirements of computer systems main memory. The IP implements the standard (NIST FIPS 197) AES cipher in XTS mode (IEEE Std 1619-2018). The SphinX family of cores covers a scalable IP with 128b and 256b key support, allowing the designer to choose the most efficient and effective core that satisfies the latency and throughput requirements.

The design is fully synchronous and supports independent, non-blocking encryption/decryption at main memory speed. SphinX is available for immediate licensing.