XIP1101B from Xiphera is a balanced Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) in Counter Mode (CTR).

The Counter mode of operation effectively turns a block cipher into a stream cipher, and provides a number of advantages from an implementation point of view. These include the ability to use the same key expansion functionality and datapath for both encryption and decryption, and the possibility to parallelize the FPGA-based implementation by unrolling and pipelining.

XIP1101B has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP1101B does not rely on any FPGA manufacturer-specific features.