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UFS Virtual Prototype

Overview

  • Software plays a very critical role in the SoC development and the design teams now spend more time writing software than building hardware.
  • In a traditional flow to system development; first hardware is designed, second Software is developed and then hardware and software is integrated.
    • As major work is Software development, this approach causes critical loss of time which effects Time-to-Market of the final product.
  • Virtual Prototype(VP) is concept in which the Software team need not wait for the actual Hardware (RTL/Silicon) to be ready.
  • The Hardware will be modelled as a Software component using SystemC language
    • VP is a key component of our delivery and the Software team can begin porting operating systems and developing device drivers, by integrating our VP models when the RTL is not ready.
    • This saves the overall SOC/System development time and makes the SW-HW integration easier, bug free
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