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Xcelium Simulation on Arm-Based Servers

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Verifying that system-on-chip (SoC) designs function correctly prior to manufacturing is a massive task requiring high-performance computing (HPC). Engineers have multiple means to address this problem because verifying every state isn't reasonable, but the most pervasive technology underlying these approaches is logic simulation. Accounting for over 70% of the EDA compute workload, SoC verification is a key driver for growth and transformation of the datacenter. Datacenters need energy-efficient platforms optimized for improved performance of a variety of different workloads that can be deployed and managed as cost effectively as possible. Arm-based server datacenters can leverage tens of thousands of multi-core CPUs to execute massive numbers of HPC workloads, such as those needed to verify SoCs for mobile, IoT, cloud, 5G, and other applications. Projects like the one in diagram are fully loading verification datacenters, but would use more HPC resources if they were available. That's where the Arm-based servers are ideal. With a greater number of cores in the same rack, datacenters can add workload capacity without affecting the physical space of the datacenter. Moreover, they can do so with reduced power consumption. Applying Xcelium Simulation and Arm Servers Having Cadence® Xcelium™ Parallel Logic Simulation running natively on Arm-based servers further extends the capacity and power benefits by more efficiently executing both high-throughput and long-latency workloads to reduce overall SoC verification time and costs. Xcelium simulation provides both a faster single-core engine, to speed up each workload in the high-throughput test group, and a multi-core engine, to reduce the runtime of long-latency workloads. As a result, Xcelium simulation is ideally suited to the high core count typical of Arm-based servers. For high-throughput tests, the high core count means that projects can run more tests in parallel on a given set of servers, so project teams can achieve better overall SoC quality and faster turnaround time to quality bug fixes. For long-latency tests, where Xcelium simulation is able to scale to all of the cores available on a server, this means 3X to 10X faster regression cycle time in the critical final days and weeks of a project cycle. By porting Xcelium simulation to Arm-based servers, Cadence is providing the electronics industry with the tooling that can exploit innovative HPC servers to speed the verification of their SoCs.

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