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IDesignSpec UVM Register Generator, IP-XACT Reader/Writer Solution

All Silicon IP

Overview

IDesignSpec™ – Create Executable Design Code From The Specification – UVM Register Generator

IDesignSpec™ is an award winning product that helps IP/SoC design architects & engineers to create simple yet powerful specification in MS Word, Excel, Libre Office or plain text. The specification is content aware and any conflict in address is checked and highlighted in the specification itself. Any change done in the specification automatically gets translated into code.

IDesignSpec (IDS) captures simple as well as special registers, signals, interrupts, sequences, and generates synthesizable RTL code and interfaces for ARM AMBA® buses like AXI, AHB, APB, AHB3Lite. IDS provides the C/C++ header files and firmware files and enable SW team to develop device driver at an early stage of the design cycle.

IDesignSpec generates a UVM based register model that covers all verification elements like covergroups, coverpoints, coverbins and illegal bins. User can also specify arbitrary hierarchical paths for blocks, register files, registers, register array and memories. Constraint expressions are translated into cover-groups and cover-points, creating bins based on the expressions specified to achieve coverage driven verification. It is also possible to generate the user-defined coverage code and also control the covergroups included in the coverage of that element in the auto-generated register or block UVM Register Model classes.

The generated RTL supports special registers. Here is a list of some of list of supported special registers -
Shadow Register, RO-WO pair at same address, Aliased Register, Locked Register, Trigger-Buffer Register (Wide register), Indirect Register, Interrupt Fields/Registers, Counters, FIFO Register, Paged Register, External (User Defined) Register.

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